发明名称 Sample Rate Converter and Rate Estimator Thereof and Rate Estimation Method Thereof
摘要 A sample rate converter receives an input signal with an input sample rate, and generates an output signal with an output sample rate. The sample rate converter includes: a rate estimator, a polynomial interpolation calculation circuit, an up sampling filter, and a down sampling filter. The rate estimator includes: a subtractor, which generates an error signal according to an input clock signal and a second order rate signal; a first order integrator, which generates a first order rate signal according to the error signal; and a second order integrator, which generates the second order rate signal according to the first order rate signal.
申请公布号 US2015145585(A1) 申请公布日期 2015.05.28
申请号 US201414498604 申请日期 2014.09.26
申请人 Tsai Kuo-Shih;Wu Tsung-Nan 发明人 Tsai Kuo-Shih;Wu Tsung-Nan
分类号 G06G7/04;G06G7/30;G06G7/18 主分类号 G06G7/04
代理机构 代理人
主权项 1. A sample rate converter for receiving an input signal with an input sample rate and generating an output signal with an output sample rate, the sample rate converter comprising: a rate estimator, for receiving an input clock signal and an output clock signal, and generating a rate signal, wherein the input clock signal corresponds the input sample rate and the output clock signal corresponds to the output sample rate, and wherein the rate signal is related to the input sample rate and the output sample rate; a polynomial interpolation calculation circuit, which is coupled to the rate estimator, for generating a polynomial interpolation signal according to a conversion data signal and the rate signal; an up sampling filter, which is coupled to the polynomial interpolation calculation circuit, for generating the conversion data signal according to the input signal; and a down sampling filter, which is coupled to the polynomial interpolation calculation circuit, for generating the output signal according to the polynomial interpolation signal; wherein the rate estimator includes: a subtractor, for generating an error signal according to the input clock signal and a second order rate signal;a first order integrator, which is coupled to the subtractor, for generating a first order rate signal according to the error signal; anda second order integrator, which is coupled to the first order integrator, for generating the second order rate signal according to the first order rate signal.
地址 HsinChu TW