| 摘要 |
A data storage device according to an embodiment of the present invention comprises a controller including a controller input and output part receiving ready/busy delay signal, and responding to a first control signal to generate a ready/busy output signal; and a memory chip including a memory input and output part receiving a chip enable delay signal, and formed to generate a chip enable output signal responding to a second control signal, wherein the ready/busy delay signal and the chip enable delay signal is transmitted through the same transmission line. |
