TIME-TO-VOLTAGE CONVERTER USING A CAPACITOR BASED DIGITAL TO ANALOG CONVERTER FOR QUANTIZATION NOISE CANCELLATION

摘要

Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.

主权项

1. A phase-locked loop (PLL) comprising:
a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal from an oscillator controlled at least in part based on a value of the combined voltage.