发明名称 データ受信回路、データ送受信システム及びデータ受信方法
摘要 <p><P>PROBLEM TO BE SOLVED: To improve the reproduction quality of audio or music by eliminating data oversupply or data undersupply at a data reception circuit when the data reception circuit is not synchronized with a data transmission circuit. <P>SOLUTION: A sampling rate converter 4 converts audio data Da synchronized with a transmission LR clock LRs to audio data Dac synchronized with a transmission LR clock LRsA. A period measurement section 1 measures a period of the transmission LR clock LRsA via a fast sampling clock fsr. A data interpolation section 2 calculates a period difference between the period of the transmission LR clock LRsA and a period of a reception LR clock LRr, and at each output timing of the reception LR clock LRr, calculates a phase of the transmission LR clock LRsA at the output timing according to the calculated period difference and interpolates the audio data Dac according to the calculated phase to generate interpolated audio data Dinsr. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5724475(B2) 申请公布日期 2015.05.27
申请号 JP20110052856 申请日期 2011.03.10
申请人 株式会社リコー 发明人 今井 幸弘
分类号 H04L7/00;H04L7/02;H04L13/08 主分类号 H04L7/00
代理机构 代理人
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