发明名称 試験条件設定方法、電流変動試験方法、及び情報処理装置
摘要 <p>A master CPU makes an execution interval b, during which CPUs are operated, common to CPUs including the master CPU and makes a stop interval a, during which the CPUs are stopped, different for each of the CPUs including the master CPU. As a result, the lengths of cycle intervals c of the CPUs constituted by the execution interval b and the stop interval a allow the ratio between the lengths of the cycle intervals c of any CPUs to be represented by two integers that are coprime to each other. Setting such lengths of the cycle intervals c of the CPUs achieves the synchronism between the shifts of all of the CPUs from a stopped state to an in-operation state and from the in-operation state to the stopped state.</p>
申请公布号 JP5724772(B2) 申请公布日期 2015.05.27
申请号 JP20110195309 申请日期 2011.09.07
申请人 发明人
分类号 G06F9/48;G06F1/26;G06F1/28;G06F1/30 主分类号 G06F9/48
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