VCSEL packaging

摘要

A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.

主权项

1. A packaging process comprising the steps of:
positioning and aligning a submount in a vacuum soldering apparatus, wherein said submount is a thermal submount, a printed circuit board or a combination thereof; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip; correcting for a curvature of the VCSEL chip surface by applying a pre-determined amount of pressure effected through a structured pad with raised regions to differentially apply controlled pressure on predetermined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature; sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.