Semiconductor device

摘要

A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.

主权项

1. A semiconductor device comprising:
a semiconductor layer; a gate insulating film above the semiconductor layer; a gate electrode on the gate insulating film; a first channel region of a first conductivity type provided on a part of a surface of the semiconductor layer below the gate insulating film; a diffusion layer of a second conductivity type different from the first conductivity type provided below the first channel region in the semiconductor layer, the diffusion layer contacting a bottom of the first channel region in a direction substantially perpendicular to a surface of the semiconductor layer, and forming a PN junction with the bottom of the first channel region; a drain of a first conductivity type provided on a side of the first channel region in the semiconductor layer; a source of a second conductivity type provided on another side of the first channel region in the semiconductor layer; a sidewall insulating film covering a side surface of the first channel region on a side of the diffusion layer, the side surface of the first channel region extending from a top surface to the bottom thereof; and a second channel region provided between the first channel region and the drain and provided on another part of the surface of the semiconductor layer below the gate insulating film, the second channel region having an impurity concentration equal to or less than 1018 cm−3.