Avoiding processing flaws in a computer processor triggered by a predetermined sequence of hardware events

摘要

A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

主权项

1. A method of avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events, the method comprising:
detecting that the predetermined sequence of hardware events is going to occur at the computer processor; performing a first power-on reset procedure by the computer processor such that the computer processor is initializing to a first state stored in computer memory in response to detecting the sequence of hardware events; and checking if a particular sequence of computer instructions is loaded at an instruction cache of the computer processor; and wherein detecting that the predetermined sequence of hardware events is going to occur at the computer processor includes detecting that the particular sequence of computer instructions is going to be executed by the computer processor.