Scalable interconnect modules with flexible channel bonding

摘要

The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

主权项

1. An integrated circuit including a serial interface with a plurality of data channels, the integrated circuit comprising:
a plurality of channel circuits, each channel circuit in the plurality of channel circuits being associated with a data channel of the plurality of data channels and performing serialization of data to be transmitted and de-serialization of data received; a first set of channel circuits that is a first subset of the plurality of channel circuits; a first data aggregation module that applies deskew aggregator logic and bonds a first subset of channel circuits from the first set of channel circuits to provide a higher-speed data channel, wherein the deskew aggregator logic performs data alignment between the channel circuits of the first subset using align characters; a first channel multiplexer circuit coupled to the first set of channel circuits and to the data aggregation module, wherein the first channel multiplexer circuit is controlled to provide data from the first subset of channel circuits to inputs of the data aggregation module; a first channel demultiplexer circuit coupled to the first data aggregation module and to the first set of channel circuits, wherein the first channel demultiplexer circuit is controlled to provide data from outputs of the first data aggregation module to the first subset of channel circuits; a second set of channel circuits that is a second subset of the plurality of channel circuits; a second data aggregation module that applies deskew aggregator logic and bonds a second subset of channel circuits from the second set of channel circuits to provide a higher-speed data channel, wherein the deskew aggregator logic performs data alignment between the channel circuits of the second subset using align characters; a second channel multiplexer circuit coupled to the second set of channel circuits and to the data aggregation module, wherein the second channel multiplexer circuit is controlled to provide data from the second subset of channel circuits to inputs of the data aggregation module; and a second channel demultiplexer circuit coupled to the second data aggregation module and to the second set of channel circuits, wherein the second channel demultiplexer circuit is controlled to provide data from outputs of the second data aggregation module to the second subset of channel circuits.