Control of inputs to a memory device

摘要

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

主权项

1. A semiconductor integrated circuit device comprising:
a command decoder configured to control a memory system by decoding a memory system input signal, the command decoder further configured to receive the memory system input signal and a control signal, and to disable the memory system input signal based at least in part on the control signal; self-refresh logic configured to provide a self-refresh signal based at least in part on an external clock enable signal, the control signal based at least in part on the self-refresh signal; and a path-gate electrically coupled to the self-refresh logic and configured to receive the external clock enable signal and provide the external clock enable signal to the self-refresh logic, the path-gate receiving power from a main voltage generator and a secondary voltage generator in the event that the main voltage generator powers off.