发明名称 Universal filter implementing second-order transfer function
摘要 An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.
申请公布号 US9041458(B2) 申请公布日期 2015.05.26
申请号 US201414339951 申请日期 2014.07.24
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Giuroiu Horia
分类号 H03B1/00;H03K5/00;H04B1/10;H03H11/12;H04R1/10;H04R3/00;H04R5/04 主分类号 H03B1/00
代理机构 代理人 Garner Jacqueline J.;Cimino Frank D.
主权项 1. A differential biquad filter circuit which receives a differential input signal and implements a predetermined transfer function to provide a differential output signal, comprising: a first amplifier having positive and negative input terminals, and positive and negative output terminals; a first input and feedback network comprising: a first resistor having first and second terminals wherein the first terminal is coupled to the negative input terminal of the first amplifier;a second resistor having first and second terminals wherein the first terminal is coupled to the positive input terminal of the first amplifier, wherein the resistance value of the first and second resistors is equal;a first capacitor coupled between the second terminal of the first resistor and the second terminal of the second resistor;a third resistor having first and second terminals, wherein the first terminal is coupled to the second terminal of the first resistor;a fourth resistor having first and second terminals, where the first terminal is coupled to the second terminal of the second resistor, wherein the resistance value of the third and fourth resistors is equal;a fifth resistor coupled between the negative input of the first amplifier and the positive output of the first amplifier;an sixth resistor coupled between the positive input of the first amplifier and the negative output of the first amplifier, wherein the resistance value of the fifth and sixth resistors is equal;a second amplifier having positive and negative input terminals, and positive and negative output terminals;a second input and feedback network comprising: a seventh resistor having a first terminal for receiving the negative side of a differential input signal, and a second terminal coupled to the negative input terminal of the second amplifier;an eighth resistor having a first terminal coupled to the positive side of differential input signal and second terminal coupled to positive input terminal of the second amplifier, wherein the resistance value of the seventh and eighth resistors is equal;a ninth resistor having first and second terminals, wherein the first terminal is coupled to the second terminal of the seventh resistor;a tenth resistor having first and second terminals, wherein the first terminal is coupled to the second terminal of the eighth, wherein the resistance value of the ninth and tenth resistors is equal;a second capacitor coupled between the second terminal of the ninth resistor and the second terminal of the tenth resistor;an eleventh resistor having a first terminal coupled to the second terminal of the ninth resistor;a twelfth resistor having a first terminal coupled to the second terminal of the tenth resistor, wherein the resistance value of the eleventh and twelfth resistors is equal;a thirteenth resistor coupled between the negative input of the second amplifier and the positive output of the second amplifier;a fourteenth resistor coupled between the positive input of the second amplifier and the negative output of the second amplifier, wherein the negative output of the second amplifier is coupled to the second terminal of the fourth resistor, wherein the resistance value of the thirteenth and fourteenth resistors is equal;wherein the positive output of the first amplifier is coupled to the positive input of the second amplifier with the tenth and the twelfth resistors there between and the negative output of the first amplifier coupled to the negative input of the second amplifier with ninth the eleventh resistors there between:a third amplifier having positive and negative input terminals, and positive and negative output terminals, wherein the positive output of the third amplifier is coupled to the second terminal of the third resistor;a third input and feedback network comprising:a fifteenth resistor coupled between the positive output terminal of the third amplifier and the negative input of the third amplifier;a sixteenth resistor coupled between the positive output terminal of the third amplifier and the negative input of the third amplifier;the negative input of the third amplifier coupled to the positive output of the first amplifier with a seventeenth resistor there between;the negative input of the third amplifier coupled to the positive output of the second amplifier with an eighteenth resistor there between;the negative input of the third amplifier coupled to the negative input terminal with a nineteenth resistor there between;the positive input of the third amplifier coupled to the negative output of the first amplifier with a twentieth resistor there between;the positive input of the third amplifier coupled to the negative output of the second amplifier with an twenty first resistor there between;the positive input of the third amplifier coupled to the positive input terminal with a twenty second resistor there between; andwherein the circuit is configured to receive a fully differential input signal and implement a predetermined transfer function to provide a filtered fully differential output signal on the output of the third amplifier.
地址 Dallas TX US