发明名称 |
Pulse generation circuit and semiconductor device |
摘要 |
Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed. |
申请公布号 |
US9041453(B2) |
申请公布日期 |
2015.05.26 |
申请号 |
US201414221523 |
申请日期 |
2014.03.21 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Miyake Hiroyuki;Toyotaka Kouhei |
分类号 |
H03K3/00;G06F1/04;H03K3/356;G09G3/36 |
主分类号 |
H03K3/00 |
代理机构 |
Nixon Peabody LLP |
代理人 |
Nixon Peabody LLP ;Costellia Jeffrey L. |
主权项 |
1. A pulse generation circuit comprising:
a first unit circuit comprising a first circuit, a second circuit, and a third circuit, the first to third circuits being connected in cascade; and a second unit circuit comprising a fourth circuit an input of which is connected to the second circuit and an output of which is connected to M (M is an integer of 2 or more) wirings, wherein the second circuit comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, wherein the second circuit is configured to output a first signal from the first output terminal to the first circuit, wherein the second circuit is configured to output a second signal from the second output terminal to the third circuit, wherein the second circuit is configured to output a third signal from the third and fourth output terminals to the fourth circuit in accordance with a fourth signal input from the first circuit, wherein the second circuit is configured to stop the output of the third signal in accordance with a fifth signal input from the third circuit, and wherein the fourth circuit is configured to generate M pulse signals from the third signal and output the M pulse signals to the M wirings, respectively. |
地址 |
Kanagawa-ken JP |