Synthesis of fast squarer functional blocks

摘要

In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.

主权项

1. An integrated circuit (IC) design tool for synthesizing logic for a squarer functional block with user selectable bit width instantiated by a register transfer level netlist, the IC design tool comprising:
code of one or more software modules stored in a storage device and executable by a processor to synthesize a gate-level netlist of a squarer functional block with a user selected bit width N, wherein the user selected bit width N is a variable, the one or more software modules including
a bitvector generator to multiply N bits of an input vector together to generate partial products of a squarer functional block for a plurality of bitvectors and to optimize a plurality of least significant bitvectors to synthesize bitvector optimization logic,a bitvector reducer coupled to the bitvector generator, the bitvector reducer to reduce the partial products in bitvectors of the squarer functional block down to a pair of final vectors and synthesize bit logic of the pair of final vectors,a dividerbit generator to generate a value of a dividerbit for a hybrid multibit adder in response to expected arrival times of bits of the pair of final vectors to be coupled into a first adder and a second adder of the hybrid multibit adder, the value of the dividerbit to balance estimated timing delays between the first adder and the second adder and couple one or more slower bits of the pair of final vectors into the first adder, anda hybrid multibit adder generator coupled to the dividerbit generator to receive the value of the dividerbit, the hybrid multibit adder generator to synthesize logic of the hybrid multibit adder including the first adder and the second adder coupled together by a carry out bit, the second adder being a different type of adder than the first adder, wherein each of a first bit width of the first adder and a second bit width of the second adder are responsive to the user selected bit width N and the dividerbit, the hybrid multibit adder coupled to the bit logic of the pair of final vectors to add the pair of final vectors together to generate a final result for the squarer functional block.