High voltage rectifier and voltage doubler using low voltage CMOS process transistors

摘要

A high voltage full wave rectifier and doubler circuit having complementary serially connected low voltage MOSFET stacks to provide high voltage capability. The state of the MOSFETs in the MOSFET stacks is controlled by means of resistors coupled between the circuit's outputs and a time varying input signal. The resistance values of the resistors are selected to maintain operation of the stacked MOSFETs below their breakdown voltages.

主权项

1. A high voltage full wave rectifier and voltage doubler circuit implemented utilizing low voltage CMOS process transistors, said rectifier and voltage doubler circuit having an input terminal, first and second voltage rails, first and second output voltage terminals and a ground terminal, said input terminal being coupled to a time varying voltage signal, said rectifier and voltage doubler circuit comprising:
a first plurality of mosfet transistors interconnected in series circuit arrangement between the first output terminal and the input terminal; a first comparator coupled across a first mosfet transistor in the first plurality of mosfet transistors wherein an output of the first comparator is coupled to the gate of the first mosfet transistor in the first plurality of mosfet transistors for controlling the state of the first mosfet transistor in the first plurality of mosfet transistors as a function of the voltage at the first output voltage terminal; a first plurality of resistors interconnected in series circuit arrangement, said first plurality of resistors coupled between the input terminal and the first voltage rail, wherein the gates of the remaining mosfet transistors in the first plurality of mosfet transistors are coupled to respective ones of the resistors in the first plurality of resistors for controlling the state of the mosfet transistor coupled thereto; a second plurality of mosfet transistors interconnected in series circuit arrangement between the second output terminal and the input terminal; a second comparator coupled across a first mosfet transistor in the second plurality of mosfet transistors wherein an output of the second comparator is coupled to the gate of the first mosfet transistor in the second plurality of mosfet transistors for controlling the state of the first mosfet transistor in the second plurality of mosfet transistors as a function of the voltage at the second output voltage terminal; a second plurality of resistors interconnected in series circuit arrangement, said second plurality of resistors coupled between the input terminal and the second voltage rail, wherein the gates of the remaining mosfet transistors in the second plurality of mosfet transistors are coupled to respective ones of the resistors in the second plurality of resistors for controlling the state of the mosfet transistor coupled thereto; a first capacitor coupled between the first output and ground; and a second capacitor coupled between the second output and ground.