| 发明名称 | Error protection for integrated circuits | ||
| 摘要 | A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism. | ||
| 申请公布号 | US9043683(B2) | 申请公布日期 | 2015.05.26 |
| 申请号 | US201313747896 | 申请日期 | 2013.01.23 |
| 申请人 | International Business Machines Corporation | 发明人 | Huott William V.;Kark Kevin W.;Massey John G.;Muller K. Paul;Rude David L.;Wolpert David S. |
| 分类号 | H03M13/00;H03M13/29;H03M13/05 | 主分类号 | H03M13/00 |
| 代理机构 | Cantor Colburn LLP | 代理人 | Cantor Colburn LLP ;Kinnaman, Jr. William A. |
| 主权项 | 1. A method for providing error detection or correction to an array of storage cells comprising: determining a sensitive direction and an insensitive direction of the storage cells; adding a first error control mechanism to the array of storage cells in the insensitive direction; and adding a second error control mechanism to the array of storage cells in the sensitive direction, wherein the storage cells comprise a length and a width that is smaller than the length, and wherein the sensitive direction is a direction perpendicular to the length of the storage cells; wherein the second error control mechanism has a higher Hamming distance than the first error control mechanism. | ||
| 地址 | Armonk NY US | ||