Functional fabric based test wrapper for circuit testing of IP blocks

摘要

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

主权项

1. A system on a chip (SoC), comprising:
an interconnect fabric over which data is transferred using a packetized multi-layer protocol; an intellectual property (IP) block, operatively coupled to the interconnect fabric; and a test wrapper, communicatively coupled to each of the interconnect fabric and the IP block; wherein, in response to receiving a test package comprising test data and/or test commands sent via one or more packets transferred over the interconnect fabric, the test wrapper is configured to provide corresponding test input data, control and/or stimulus signals to the IP block to perform one or more test operations on circuitry in the IP block.