Data bus efficiency via cache line usurpation

摘要

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

主权项

1. A device comprising:
a cache memory, the cache memory comprising one or more cache memory locations; a connection to a main memory, the main memory being external to the device and comprising one or more main memory locations; and a control unit operably coupled to the cache memory, wherein the control unit is operable to:
determine whether a main memory location is already associated with a cache memory location,access data from the main memory location,determine whether the data from the main memory location is required for a future computation,write the data from the main memory location to the cache memory location, if the data is required for a future computation; andinitialize the cache memory location, if the data is not required for a future computation.