Modeling gate resistance of a multi-fin multi-gate field effect transistor

摘要

The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element.

主权项

1. A modeling method comprising:
accessing, by a computer from a memory, a design for a field effect transistor, said field effect transistor comprising:
a gate structure with a horizontal portion traversing multiple semiconductor fins and with vertical portions adjacent to opposing sides of said semiconductor fins; andat least one gate contact to said horizontal portion; constructing, by said computer and based on said design, a resistive network to define all resistive elements within said gate structure, said resistive elements comprising:
first resistive elements connected in series within said horizontal portion;second resistive elements within said vertical portions and connected in parallel by said horizontal portion; andat least one third resistive element within said at least one gate contact; and determining, by said computer and based on said resistive network, a total resistance associated with said gate structure, said total resistance being based on resistance contributions from said first resistive elements, said second resistive elements and said at least one third resistive element, and each resistance contribution of each resistive element being based on a resistance value of said resistive element, a square of a first fraction of current from said semiconductor fins entering said resistive element, a square of a second fraction of said current from said semiconductor fins exiting said resistive element and a production of said first fraction and said second fraction, said first fraction and said fraction depending upon what portion of said current from said semiconductor fins flows through each gate contact and upon a location of said resistive element within said resistive network relative to each gate contact.