Feedback for delay lock loop

摘要

The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.

主权项

1. A serializer deserializer system (SerDeS) comprising:
a delay-lock loop system comprising:
a phase detector configured to generate an up signal and a down signal based on a reference clock signal and a feedback clock signal;a charge pump configured to generate a reference voltage using the up signal and the down signal from the phase detection;a voltage regulator configured to generate a drive voltage based on the reference voltage; anda delay module having N delay lines, the N delay lines having a first delay line D0 and a last delay line Dn-1, the delay module being configured to provide a positive current compensation value and a negative current compensation value using a first common feedback structure, the first common feedback structure having a first input based on the phase difference between the first delay line D0 and the last delay line Dn-1 and a second input based on two adjacent delay lines of the N delay lines; anda receiver coupled of the delay lock loop.