发明名称 Method and apparatus for performing logical compare operation
摘要 A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
申请公布号 US9043379(B2) 申请公布日期 2015.05.26
申请号 US201213656636 申请日期 2012.10.19
申请人 Intel Corporation 发明人 Kapoor Rajiv;Zohar Ronen;Buxton Mark;Sperber Zeev;Gottlieb Koby
分类号 G06F7/50;G06F9/30;G06F7/02 主分类号 G06F7/50
代理机构 Mnemoglyphics, LLC 代理人 Mnemoglyphics, LLC ;Mennemeier Lawrence M.
主权项 1. A processor, comprising: a cache to store data; instruction decode logic to decode one or more instructions; a data register file including a set of 128-bit packed data registers, the packed data registers to store packed single-precision floating point (SPFP) data elements including a first SPFP data element and a second SPFP data element; and an execution unit to execute a comparison instruction to compare the first SPFP data element and the second SPFP data element and to responsively set at least one bit of data to indicate a result of the comparison, the at least one bit of data to control operation of a branch instruction.
地址 Santa Clara CA US