| 发明名称 | Circuit and method | ||
| 摘要 | Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input. | ||
| 申请公布号 | US9041576(B2) | 申请公布日期 | 2015.05.26 |
| 申请号 | US201213976649 | 申请日期 | 2012.12.20 |
| 申请人 | Intel Mobile Communications GmbH | 发明人 | Klepser Bernd-Ulrich;Scholz Markus;Boos Zdravko;Mayer Thomas |
| 分类号 | H03M1/66;H03M1/74;H04L27/20;H04L27/36;H03M1/82 | 主分类号 | H03M1/66 |
| 代理机构 | Eschweiler & Associates, LLC | 代理人 | Eschweiler & Associates, LLC |
| 主权项 | 1. A circuit, comprising: a digital-to-time converter comprising a high-frequency input configured to receive a high-frequency signal, a digital input configured to receive a first digital signal, and a high-frequency output configured to provide a chronologically delayed version of the high-frequency signal; and an oscillator arrangement configured to provide the high-frequency signal having a phase-locked loop configured to provide a frequency of the high-frequency signal; and wherein the digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input. | ||
| 地址 | Neubiberg DE | ||