Three-dimensional vertically interconnected structure and fabricating method thereof

摘要

The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.

主权项

1. A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of:
S1, conducting lithography on a surface of a single layer of silicon wafer or chip which has or has not undergone a thinning process to form photo-resist mask for annular patterns, then sequentially etching a first dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape; S2, depositing a barrier layer and a seed layer to cover an inside wall of the first concave, and then copper electroplating to fill the first concave, for forming a first electrical conductive ring; S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a second dielectric layer and a metallic interconnection layer; S4, etching the second dielectric layer of the redistribution layer and the first dielectric layer of the wafer or chip sequentially to form a first through-silicon-via (TSV) inside the first electrical conductive ring, wherein the first TSV has the same radius and center as the inner ring of the first electrical conductive ring; S5, sequentially stacking single layers of wafers or chips which have completed steps S1-S4 and aligning the same, and adjacent wafers or chips being adhered to each other by using organics or metallic solders; S6, depositing a seed layer and electroplating copper on one side of the multi-stacked layers of wafers or chips to seal a first through layers of wafers or chips hole that is constituted of vertically aligned TSVs; filling the first through layers of wafers or chips holes which penetrate the multi-layered stacks from bottom to top with copper electroplating to form a first micro electrical conductive pole, and removing the electroplated copper and seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.