Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof

摘要

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

主权项

1. A method for fabricating stacked microelectronic packages, comprising:
arranging microelectronic device panels in a panel stack, each microelectronic device panel comprising a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom; forming trenches in the panel stack, the trenches having sidewalls through which the plurality of package edge conductors are exposed; dispensing a metal-containing epoxy into the trenches in sufficient quantity to substantially fill the trenches and yield a plurality of epoxy-filled trenches separating the panel stack into partially-completed stacked microelectronic packages to produce unpatterned metal-containing epoxy layers contacting the plurality of package edge conductors, the panel stack separated along saw lanes extending through the epoxy-filled trenches to impart the unpatterned metal-containing epoxy layers with exposed sidewall surfaces; and patterning the unpatterned metal-containing epoxy layers to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic packages, wherein selected portions of the unpatterned metal-containing epoxy layers are removed at the exposed sidewall surfaces during patterning.