Circuit and method of clocking multiple digital circuits in multiple phases

摘要

A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

主权项

1. A circuit comprising:
a power supply terminal; a clock parsing circuit configured to produce multiple clock signals having different phases; a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal, each digital circuit including an input to receive data and logic to process the data, each digital circuit responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the power supply terminal to process the data to produce a data output; a control circuit coupled to the clock parsing circuit and the plurality of digital circuits, the control circuit to selectively control the clock parsing circuit to provide a clock signal of the multiple clock signals having a clock period that differs from that of others of the multiple clock signals; and an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits provided to one or more destination circuits, the output management timing circuit including an intermediate clock domain circuit having relaxed input timing constraints and configured to re-clock each of the digital outputs to an intermediate clock frequency.