Partial reconfiguration and in-system debugging

摘要

Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

主权项

1. An apparatus comprising:
a first region of logic; a second region of logic for configuring between a first logic design and a second logic design; and a first port for receiving at least one signal from the second region of logic and providing the signal to the first region of logic, wherein the first logic design includes a first probe point associated with a first node of the first logic design, the second logic design includes a second probe point associated with a second node of the second logic design, and a signal associated with the first or second nodes provided to the first port based on the logic design configured in the second region of logic.