发明名称 |
Analog-to-digital conversion |
摘要 |
An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source. The feedback circuit comprises a second differential amplifier OP1 with a first input connected to a node 46 on the first branch and a second input connected to a reference voltage VB such that the node on the first branch is maintained at a substantially constant voltage. |
申请公布号 |
US9041581(B2) |
申请公布日期 |
2015.05.26 |
申请号 |
US201414295267 |
申请日期 |
2014.06.03 |
申请人 |
CMOSIS BVBA |
发明人 |
Wolfs Bram |
分类号 |
H03M1/36;H03M1/18 |
主分类号 |
H03M1/36 |
代理机构 |
Sulzer, Green & Taylor PLLC |
代理人 |
Sulzer, Green & Taylor PLLC |
主权项 |
1. An analog-to-digital conversion apparatus comprising:
a plurality of analog-to-digital converters; a ramp generator which is arranged to generate a ramp signal for distribution to the plurality of analog-to-digital converters; wherein each of the analog-to-digital converters comprises:
an analog signal input for receiving an analog signal level;a ramp signal input for receiving the ramp signal;a control stage which is arranged to compare the ramp signal with the analog signal level received at the analog signal input and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter, the control stage comprising:
a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output;a variable biasing current source for biasing the first differential amplifier;a feedback circuit for controlling the variable biasing current source, wherein the feedback circuit comprises a second differential amplifier with a first input connected to a node on the first branch and a second input connected to a reference voltage such that the node on the first branch is maintained at a substantially constant voltage during all comparison states of the comparator. |
地址 |
Antwerp BE |