发明名称 SYSTEMS AND METHODS FOR DIRECT DATA ACCESS IN MULTI-LEVEL CACHE MEMORY HIERARCHIES
摘要 Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.
申请公布号 US2015143047(A1) 申请公布日期 2015.05.21
申请号 US201414549065 申请日期 2014.11.20
申请人 Green Cache AB 发明人 HAGERSTEN Erik;SEMBRANT Andreas;BLACK-SCHAFFER David;KAXIRAS Stefanos
分类号 G06F12/10;G06F12/08 主分类号 G06F12/10
代理机构 代理人
主权项 1. A cache memory system comprising: a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory; a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in said cache location buffer; and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in said cache location buffer; and wherein, responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables for one of said first and second cache memories which enables access to said cacheline without performing a tag comparison at the one of the first and second cache memories.
地址 Uppsala SE
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