FINFET CELL ARCHITECTURE WITH POWER TRACES

摘要

A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

主权项

1. An integrated circuit, comprising:
a substrate; a first set of semiconductor fins in a first region of the substrate, including outer fins on opposing outside edges of the first set; a first isolation feature parallel to the first set of semiconductor fins; a second isolation feature located in the first region between the outer fins of the first set of semiconductor fins; a patterned gate conductor layer including a plurality of first region gate traces overlying the first set, the plurality of first gate traces including;
a first gate trace extending from a position proximate a first outer fin of the first set and terminating at a position proximate the second isolation feature; anda second gate trace extending from a position proximate the first outer fin to a position proximate a second outer fin, opposite the first outer fin.