Thyristor Memory Cell Integrated Circuit

摘要

A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

主权项

1. A semiconductor memory device comprising:
an array of memory cells formed on a substrate, each given memory cell including a resistive load element and a thyristor device that define a switchable current path through the resistive load element and the thyristor device of the given memory cell, wherein the resistive load element is realized from a phase change material that can be selectively programmed into one of a high resistive state and a low resistive state by current that flows through the switchable current path of the given memory cell, and wherein the state of the switchable current path of the given memory cell represents a volatile bit value stored by the given memory cell; at least one word line corresponding to a first set of memory cells of the array, wherein the word line is coupled to the switchable current path through the resistive load element and thyristor device for the first set of memory cells of the array; and at least one bit line corresponding to a second set of memory cells of the array, wherein the bit line is coupled to a modulation doped quantum well interface of the thyristor device for the second set of memory cells of the array; wherein each given memory cell is accessed to detect the volatile bit value stored by the given memory cell by applying a voltage pulse to the word line coupled to the switchable current path through the resistive load element and thyristor device of the given memory cell in conjunction with sensing voltage of the bit line coupled to the modulation doped quantum well interface of the thyristor device of the given memory cell.