| 发明名称 |
CACHE CONTROL APPARATUS AND METHOD |
| 摘要 |
Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache. |
| 申请公布号 |
US2015143045(A1) |
申请公布日期 |
2015.05.21 |
| 申请号 |
US201414253466 |
申请日期 |
2014.04.15 |
| 申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
HAN Jin Ho;KWON Young Su;SHIN Kyoung Seon |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A cache control apparatus comprising:
a first level cache configured to store data in a memory; a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction; a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core; and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache. |
| 地址 |
Daejeon KR |
