| 摘要 |
The purpose of the present invention is, using Surrounding Gate Transistors (SGT) which are vertical transistors, to provide a semiconductor device which configures a decoder circuit for memory selection and which occupies a small area. In a decoder circuit configured using a plurality of MOS transistors disposed in m rows and n columns, the MOS transistors configuring the decoder circuit are formed upon a planar silicon layer formed upon a substrate, with drains, gates, and sources being disposed vertically. Said gates surround silicon columns, and said planar silicon layer comprises a first active area having a first conductivity type and a second active area having a second conductivity type, with the active areas being connected to each other through a silicon layer formed upon the planar silicon layer surface. Thus, a semiconductor device which configures a decoder circuit of a small area is provided. |
