COMPUTER MEMORY POWER MANAGEMENT

摘要

A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.

主权项

1. A computer memory system comprising:
error correcting code decoder configured to:
detect a data error a first memory array of a computer memory system using an error correcting code;associate a first chip mark with the first memory array; andhandle the data error in the first memory array; and power switching logic configured to:
select, in response to a power saving instruction, a second memory array of the computer memory system.