APPARATUS AND METHODS FOR PARTITIONING AN INTEGRATED CIRCUIT DESIGN INTO MULTIPLE PROGRAMMABLE DEVICES

摘要

Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments include a bridge in each programmable logic device for providing synchronization and deterministic latency of packets sent between the programmable devices.