发明名称 METHOD IN A MEMORY MANAGEMENT UNIT FOR MANAGING ADDRESS TRANSLATIONS IN TWO STAGES
摘要 A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.
申请公布号 US2015143072(A1) 申请公布日期 2015.05.21
申请号 US201414526686 申请日期 2014.10.29
申请人 STMicroelectronics International N.V. 发明人 Sibert Herve;Pallardy Loic
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
主权项 1. A method of managing address translations using a memory management unit, comprising: performing address translations between a virtual address space and an intermediate physical address space, using a processor and a first address translation table associated with a first cache memory; and performing address translations between the intermediate physical address space and a physical address space, using the processor and a second address translation table associated with a second cache memory.
地址 Amsterdam NL