发明名称 METHOD OF MANUFACTURING MULTILAYER WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board capable of suppressing plating voids in an electrolytic field plating layer even for a via hole aperture having a diameter same as an insulating layer thickness.SOLUTION: A method of manufacturing a multilayer wiring board including: a step (1) of providing, by using the conformal method or the direct laser method, a via hole aperture from metal foil for upper layer wiring to inner layer wiring, a metal foil projection for the upper layer wiring formed at an opening of this via hole aperture, and a lower space formed between the metal foil projection and an inner wall of the via hole aperture; and a step (2) of filling the via hole aperture by forming an electrolytic field plating layer in the via hole aperture and on the metal foil for the upper layer wiring. The filling of the via hole aperture by forming the electrolytic field plating layer in the step (2) is performed so that a current density of the electrolytic field plating is reduced once in the middle of the electrolytic field plating and increased again.
申请公布号 JP2015097251(A) 申请公布日期 2015.05.21
申请号 JP20140147754 申请日期 2014.07.18
申请人 HITACHI CHEMICAL CO LTD 发明人 YOSHIDA NOBUYUKI
分类号 H05K3/46 主分类号 H05K3/46
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