SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN

摘要

The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

主权项

1. A method implemented in a programmable system for clock gating synthesis, comprising:
identifying in an integrated circuit design having pipelined flip-flops having an expected utilization below a specified threshold; gating the identified flip flops such that they can be shut down when not in use, said gating being performed by extraction of a stability condition for each identified flip flop in the design.