| 发明名称 |
Low Leakage State Retention Synchronizer |
| 摘要 |
Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units. |
| 申请公布号 |
US2015138905(A1) |
申请公布日期 |
2015.05.21 |
| 申请号 |
US201314083185 |
申请日期 |
2013.11.18 |
| 申请人 |
JAYAPAL Senthilkumar;SCHUELEIN Mark E.;BHATIA Deepak |
发明人 |
JAYAPAL Senthilkumar;SCHUELEIN Mark E.;BHATIA Deepak |
| 分类号 |
H03K19/003;G11C5/14 |
主分类号 |
H03K19/003 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic unit coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units. |
| 地址 |
Penang MY |
