发明名称 |
METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY |
摘要 |
A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page. |
申请公布号 |
US2015143198(A1) |
申请公布日期 |
2015.05.21 |
申请号 |
US201314081645 |
申请日期 |
2013.11.15 |
申请人 |
QUALCOMM Incorporated |
发明人 |
CHUN Dexter;KIM Jung Pill;SHIN Hyunsuk;SUH Jungwon |
分类号 |
G06F11/10;G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
1. A system comprising:
a system memory comprising an error detection circuit, the system memory comprising volatile memory; a controller coupled to the system memory; a processor coupled to the controller; a re-mapper coupled to the processor and the system memory, the re-mapper to store mappings of page addresses; a non-volatile memory; and a memory comprising stored instructions, wherein in response to the error detection circuit detecting a multiple-bit error in a page residing in the system memory, the page having a first physical address, the stored instructions when executed by the processor cause the system to perform a procedure comprising:
looking up in a page table if a golden page associated with the first physical address resides in the non-volatile memory;copying the golden page to a redundant page in the system memory provided the golden page resides in the non-volatile memory, the redundant page having a second physical address; andconfiguring the re-mapper to map the first physical address to the second physical address when the processor performs a memory operation indicating the first physical address, wherein the re-mapper provides the second physical address to the system memory. |
地址 |
San Diego CA US |