DATA TRANSFER BETWEEN CLOCK DOMAINS

摘要

An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

主权项

1. An arrangement for transferring a data signal from a first clock domain to a second clock domain in a digital system, wherein the first clock domain comprises a first clock having a frequency less than a frequency of a second clock in the second clock domain, the arrangement being configured to:
transfer the data signal from the first clock domain to the second clock domain; detect whether a predetermined transition occurs in the first clock within a predetermined period of time, using a detecting circuit portion clocked by the second clock; and transfer the data signal from the first clock domain to the second clock domain again if the detecting means detects said predetermined transition in the first clock within the predetermined period of time.