SUPPORT FOR IOAPIC INTERRUPTS IN AMBA-BASED DEVICES

摘要

One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

主权项

1. A computing system for supporting IOAPIC interrupts between an IO device and the computing system, wherein the IO device is an AMBA® compliant IO device, and wherein the computing system is a PCIe compliant computing system, the computing system comprising:
an x86 compatible host system including:
an x86 compatible processor;memory;a PCIe root complex (RC); anda PCIe bus to which the processor, memory, and PCIe RC are communicatively connected; an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC of the host system through a PCIe link, the PCIe EP of the interconnect chip being connected to an AMBA® bus, wherein the interconnect chip communicates with the IO device via the AMBA® bus in an AMBA® compliant manner, and communicates with the host system in a PCIe compliant manner, by: receiving a command from the processor for the IO device; sending the command to the IO device over the AMBA® bus; receiving a response from the IO device over the AMBA® bus; upon receiving the response, sending over the AMBA® bus and over the PCIe link one or more DMA operations to the memory of the host system; and after sending the DMA operations to the memory, sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.