发明名称 昇降圧回路及び昇降圧回路制御方法
摘要 <p>A voltage boosting/lowering circuit according to an aspect of the present invention includes an output voltage generation circuit 15 that includes a switch element 2 connected between an input terminal 1 and a choke coil 3 and a switch element 7 connected between the choke coil 3 and a ground, and generates an output voltage by switching the switch elements 2 and 7 between an on-state and an off-state and thereby boosting/lowering an input voltage input to the input terminal 1, a first switch control unit that outputs a first pulse signal to the switch element 2, a duty detection circuit 32 that detects a duty of the first pulse signal, and a second switch control unit that outputs a second pulse signal to the switch element 7 according to the detected duty.</p>
申请公布号 JP5721403(B2) 申请公布日期 2015.05.20
申请号 JP20100257951 申请日期 2010.11.18
申请人 发明人
分类号 H02M3/155 主分类号 H02M3/155
代理机构 代理人
主权项
地址