发明名称 Clock buffer
摘要 <p>A tuneable buffer circuit for use in a clock tree has multiple buffers (40, 42) in parallel, each buffer having a grounding function (48), and also a bypass switch (46) in parallel with the buffers (40, 42). The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.</p>
申请公布号 EP2765474(B1) 申请公布日期 2015.05.20
申请号 EP20130154865 申请日期 2013.02.12
申请人 NXP B.V. 发明人 SHARMA, VIBHU;MEIJER, RINZE;PINEDA DE GYVEZ, JOSÉ
分类号 H03K19/0185;G06F1/10;H03K19/00;H03K19/0175 主分类号 H03K19/0185
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