发明名称 通信機
摘要 <p>The present invention is directed to reduction of operation amount of likelihood calculation (LLR calculation) in a communication apparatus for performing communications using an extended mapping in which a plurality of bit sequences are assigned to a single symbol point. A receiving unit receives a signal which is transmitted from a transmitting unit by using the extended mapping. A repetition process unit decodes the received signal from the receiving unit by calculating an LLR of the received signal and performing a repetition process. In this case, the LLR is calculated for every bit using a MAX-LOG approximation and a thus-derived approximation formula is multiplied by weighting factors corresponding to proportions of“0”and“1”in each bit assigned to a symbol point closest to the received signal.</p>
申请公布号 JP5721486(B2) 申请公布日期 2015.05.20
申请号 JP20110060821 申请日期 2011.03.18
申请人 发明人
分类号 H04L27/18;H03M13/25;H03M13/39;H04L27/00 主分类号 H04L27/18
代理机构 代理人
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