NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY

摘要

In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.