Semiconductor device

摘要

A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal.

主权项

1. A device comprising:
a first clock dividing unit that receives a first clock signal and generates a plurality of second clock signals in response to the first clock signal, the second clock signals being different in phase from each other; a second clock dividing unit that receives a third clock signal antecedent in phase to the first clock signal and generates a plurality of fourth clock signals in response to the third clock signal, the fourth clock signals being different in phase from each other, and each of the fourth clock signals being related to an associated one of the second clock signals; a first control circuit that generates a first control signal in response to the first clock signal; and a second control circuit that receives the second clock signals, the fourth clock signals and the first control signal, and generates a second control signal in response to the first control signal, one of the second clock signals and one of the fourth clock signals that is related to the one of the second clock signals.