| 发明名称 |
Semiconductor device having penetration electrodes penetrating through semiconductor chip |
| 摘要 |
Disclosed herein is a semiconductor device that includes: a first circuit formed on a chip having a main surface; first to nth penetration electrodes penetrating through the chip, where n is an integer more than 1; first to nth main terminals arranged on the main surface of the chip and vertically aligned with the first to nth penetration electrodes, respectively, each of kth main terminal being electrically connected to k+1th penetration electrode, where k is an integer more than 0 and smaller than n, and the nth main terminal being electrically connected to the first penetration electrode; a sub-terminal arranged on the main surface of the chip; and a selection circuit electrically connected to predetermined one of the first to nth main terminals, the sub-terminal, and the first circuit, wherein the selection circuit connects the first circuit to one of the predetermined main terminal and the sub-terminal. |
| 申请公布号 |
US9035444(B2) |
申请公布日期 |
2015.05.19 |
| 申请号 |
US201213493578 |
申请日期 |
2012.06.11 |
| 申请人 |
PS4 Luxco S.a.r.l. |
发明人 |
Sato Homare |
| 分类号 |
H01L23/02;H01L25/065;H01L23/48 |
主分类号 |
H01L23/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor device comprising:
a first circuit formed on a first chip having a main surface; first to nth penetration electrodes penetrating through the first chip, where n is an integer more than 1; first to nth main terminals arranged on the main surface of the first chip and vertically aligned with the first to nth penetration electrodes, respectively, each of kth main terminal being electrically connected to k+1th penetration electrode and not being electrically connected to a kth penetration electrode, where k is an integer more than 0 and smaller than n, and the nth main terminal being electrically connected to the first penetration electrode and not being electrically connected to the nth penetration electrode; a sub-terminal arranged on the main surface of the first chip; and a selection circuit electrically connected to predetermined one of the first to nth main terminals, the sub-terminal, and the first circuit, wherein the selection circuit connects the first circuit to one of the predetermined main terminal and the sub-terminal. |
| 地址 |
Luxembourg LU |
