发明名称 Layout schemes for cascade MOS transistors
摘要 A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.
申请公布号 US9035389(B2) 申请公布日期 2015.05.19
申请号 US201213657389 申请日期 2012.10.22
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Wen Chin-Hua;Chou Wen-Shen
分类号 H01L21/70;H01L27/12;H01L27/088;H01L29/06;H01L23/528 主分类号 H01L21/70
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A device comprising: a first Metal-Oxide-Semiconductor (MOS) device; a second MOS device cascaded with the first MOS device to form a first finger, wherein a drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region; a third MOS device; a fourth MOS device cascaded with the third MOS device to form a second finger, wherein a drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region, wherein the first and the second common source/drain regions are electrically disconnected from each other, and wherein: sources of the first and the third MOS devices are interconnected;drains of the second and the fourth MOS devices are interconnected;gates of the first and the third MOS devices are interconnected; andgates of the second and the fourth MOS devices are interconnected; and a power bus in a metal layer and forming a continuous metal overlapping both the source of the first MOS device and the first common source/drain region, wherein the source of the first MOS device is connected to the power bus, and the first common source/drain region and the second common source/drain region are electrically disconnected from the power bus.
地址 Hsin-Chu TW