Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system

摘要

A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

主权项

1. A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer connected to outputs of a plurality of analog-to-digital converters (ADCs) based on time-interleaved successive approximation registers, the VPDA MIMO equalizer comprising:
a plurality of sub-equalizers classified into a first sub-equalizers group and a second sub-equalizers group, wherein each of a plurality of sub-equalizers included in the first sub-equalizers group is connected to outputs of a first ADC group and each of a plurality of sub-equalizers included in the second sub-equalizers group is connected to outputs of a second ADC group; and a decision unit configured to determine recovered data using an output symbol of the plurality of sub-equalizers, wherein one sub-equalizer included in the first sub-equalizers group relates to other one sub-equalizer included in the second sub-equalizers group, and the recovered data is determined by the decision unit based on outputs of the one sub-equalizer and the other one sub-equalizer, wherein each of the plurality of sub-equalizers comprises a plurality of additional-equalizers for distributed arithmetic, and each of the additional-equalizers corresponds to one of bits according to a resolution of the ADCs.