发明名称 |
Nonvolatile semiconductor memory device |
摘要 |
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region provided with a plurality of memory cells, and a peripheral region provided around the memory cell region. The device includes: a foundation layer provided in the memory cell region and in the peripheral region, the foundation layer including a plurality of wiring layers and a plurality of device elements; and a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers and a plurality of intermediate layers alternately stacked. The peripheral region includes an interlayer insulating film provided on the stacked body; and an electrode pad provided on the interlayer insulating film and electrically connected to one of the plurality of wiring layers. |
申请公布号 |
US9035371(B2) |
申请公布日期 |
2015.05.19 |
申请号 |
US201313848232 |
申请日期 |
2013.03.21 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Nakajima Hiroomi |
分类号 |
H01L29/792;H01L27/088;H01L27/115;H01L23/00 |
主分类号 |
H01L29/792 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A nonvolatile semiconductor memory device including a memory cell region provided with a plurality of memory cells, and a peripheral region provided around the memory cell region, the device comprising:
a foundation layer provided in the memory cell region and in the peripheral region, the foundation layer including a plurality of wiring layers and a plurality of device elements; and a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers and a plurality of intermediate layers alternately stacked, the memory cell region including:
a first channel body layer penetrating through the stacked body and the first channel body layer extending from an upper surface of the stacked body to a lower surface of the stacked body;a memory film provided between first channel body layer and each of the plurality of electrode layers;a pair of select gate electrodes provided on the stacked body;a second channel body layer penetrating through each of the pair of select gate electrodes and the second channel body layer being connected to the first channel body layer; anda gate insulating film provided between each of the pair of select gate electrodes and the second channel body layer, and the peripheral region including:an interlayer insulating film provided on the stacked body; andan electrode pad provided on the interlayer insulating film, a bonding wire being capable of being bonded to the electrode pad, at least one of the plurality of wiring layers being provided below the electrode pad. |
地址 |
Tokyo JP |