Memory module with circuit providing load isolation and noise reduction

摘要

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

主权项

1. A memory module operable to communicate data with a system memory controller via a memory bus in response to address and control signals from the system memory controller, comprising:
a printed circuit board comprising at least one connector configured to be operatively coupled to the memory bus, the at least one connector including a plurality of edge connections distributed along one or more edges of the printed circuit board; a plurality of memory devices on the printed circuit board, the plurality of memory devices being arranged in multiple ranks, including a first rank and a second rank, each rank comprising an independent set of memory devices that can be accessed by the system memory controller to access a full bit-width of the memory bus; a circuit coupled between the at least one connector and the plurality of memory devices, the circuit comprising a first set of ports coupled to respective ones of the plurality of edge connections, the first set of ports including a set of bidirectional ports for conducting data signals, each port of the set of bidirectional ports in the first set of ports including a programmable impedance matching circuit having at least one variable impedance that can be programmed to match a characteristic impedance of a corresponding signal path in the system, the circuit further comprising a second set of ports coupled to the plurality of memory devices, the second set of ports including a first subset of ports coupled to the first rank and a second subset of ports coupled to the second rank the circuit further comprising a switching sub-circuit configured to operatively couple the first subset of ports to respective ones of the set of bidirectional ports and to isolate the second subset of ports from the set of bidirectional ports in response to a set of address and control signals from the system memory controller, the set of address and control signals causing the memory module to select the first rank and not the second rank for memory access by the system memory controller; and control circuitry configured to control the switching sub-circuit and the programmable impedance matching circuits in response to one or more signals in the address and control signals.